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128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
x x
IDT71V3576S IDT71V3578S IDT71V3576SA IDT71V3578SA
Features
128K x 36, 256K x 18 memory configurations Supports high system speed: Commercial and Industrial: - 150MHz 3.8ns clock access time - 133MHz 4.2ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O Optional - Boundary Scan JTAG Interface (IEEE 1149.1 compliant) Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA)
Description
The IDT71V3576/78 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V3576/78 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The IDT71V3576/78 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA).
x x
x x x x
x
Pin Description Summary
A0-A17 CE CS0, CS1 OE GW BWE BW1, BW2, BW3, BW4 CLK ADV ADSC ADSP LBO TMS TDI TCK TDO TRST ZZ I/O0-I/O31, I/OP1-I/OP4 VDD, VDDQ VSS
(1)
Address Inputs Chip Enable Chip Selects Output Enable Global Write Enable Byte Write Enable Individual Byte Write Selects Clock Burst Address Advance Address Status (Cache Controller) Address Status (Processor) Linear / Interleaved Burst Order Test Mode Select Test Data Input Test Clock Test Data Output JTAG Reset (Optional) Sleep Mode Data Input / Output Core Power, I/O Power Ground
Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Input I/O Supply Supply
Synchronous Synchronous Synchronous Asynchronous Synchronous Synchronous Synchronous N/A Synchronous Synchronous Synchronous DC Synchronous Synchronous N/A Synchronous Asynchronous Asynchronous Synchronous N/A N/A
5279 tbl 01
NOTE: 1. BW3 and BW4 are not applicable for the IDT71V3578.
JUNE 2003
1
DSC-5279/03
(c)2003 Integrated Device Technology, Inc.
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol A0-A17 ADSC ADSP Pin Function Address Inputs Address Status (Cache Controller) Address Status (Processor) Burst Address Advance I/O I I I Active N/A LOW LOW Description Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK and ADSC Low or ADSP Low and CE Low. Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the address registers with new addresses. Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address registers with new addresses. ADSP is gated by CE. Synchronous Address Advance. ADV is an active LOW input that is use d to advance the internal burst counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not incremented; that is, there is no address advance. Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are blocked and only GW can initiate a write cycle. Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte write causes all outputs to be disabled. Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V3576/78. CE also gates ADSP. This is the clock input. All timing references for the device are made with respect to this input. Synchrono us active HIGH chip select. CS0 is used with CE and CS1 to enable the chip. Synchro nous active LOW chip select. CS1 is used with CE and CS0 to enable the chip. Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of CLK. GW supersedes individual byte write enables. Synchro nous data input/output (I/O) pins. Both the data input path and data output path are registered and triggered by the rising edge of CLK. Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state while the device is operating. Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state. Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup. Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal pullup. Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup. Serial o utput of registers placed between TDI and TDO. This output is active depending on the state of the TAP controller. Optional Asynchrono us JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset occurs automatically at po wer up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can be left floating. This pin has an internal pullup. Only available in BGA package. Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3576/78 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull down. 3.3V core power supply. 3.3V I/O Supply. Ground. NC pins are not electrically connected to the device.
5279 tbl 02
ADV
I
LOW
BWE
Byte Write Enable Individual Byte Write Enables Chip Enable Clock Chip Select 0 Chip Select 1 Global Write Enable Data Input/Output
I
LOW
BW1-BW4 CE CLK CS0 CS1 GW I/O0-I/O31 I/OP1-I/OP4 LBO
I I I I I I I/O
LOW LOW N/A HIGH LOW LOW N/A
Linear Burst Order
I
LOW
OE TMS TDI TCK TDO
Output Enable Test ModeSelect Test Data Input Test Clock Test DataOutput JTAG Reset (Optional)
I I I I O
LOW N/A N/A N/A N/A
TRST
I
LOW
ZZ VDD VDDQ VSS NC
Sleep Mode Power Supply Power Supply Ground No Connect
I N/A N/A N/A N/A
HIGH N/A N/A N/A N/A
NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42 2
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO ADV
CEN Burst Sequence INTERNAL ADDRESS
CLK ADSC ADSP
CLK EN Binary Counter CLR
2
Burst Logic
17/18 A0* A1*
Q0 Q1
128K x 36/ 256K x 18BIT MEMORY ARRAY
2 17/18
A0 - A16/17 GW BWE BW1
A0,A1
ADDRESS REGISTER Byte 1 Write Register
A2-A17
36/18
36/18
Byte 1 Write Driver
9
Byte 2 Write Register Byte 2 Write Driver
BW2
Byte 3 Write Register
9
Byte 3 Write Driver
BW3
Byte 4 Write Register
9
Byte 4 Write Driver
BW4
9
OUTPUT REGISTER
CE CS0 CS1
D
Q Enable Register
DATA INPUT REGISTER
CLK EN
ZZ
Powerdown D Q Enable Delay Register
OE OUTPUT BUFFER
OE I/O0 -- I/O31 I/OP1 -- I/OP4
36/18
,
5279 drw 01
TMS TDI TCK TRST (Optional)
JTAG (SA Version)
TDO
6.42 3
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM(2) VTERM(3,6) VTERM(4,6) VTERM(5,6) Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Commercial Operating Temperature Industrial Operating Temperature TBIAS TSTG PT IOUT Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Commercial & Industrial -0.5 to +4.6 -0.5 to VDD -0.5 to VDD +0.5 -0.5 to VDDQ +0.5 -0 to +70 -40 to +85 -55 to +125 -55 to +125 2.0 50 Unit V V
Recommended Operating Temperature and Supply Voltage
Grade Commercial Industrial Temperature(1) 0C to +70C -40C to +85C VSS 0V 0V VDD 3.3V5% 3.3V5% VDDQ 3.3V5% 3.3V5%
5279 tbl 04
NOTES: 1. TA is the "instant on" case temperature.
V V
o
Recommended DC Operating Conditions
Symbol VDD Parameter Core Supply Voltage I/O Supply Voltage Supply Voltage Input High Voltage - Inputs Input High Voltage - I/O Input Low Voltage Min. 3.135 3.135 0 2.0 2.0 -0.3
(2)
C C C C
Typ. 3.3 3.3 0
____ ____ ____
Max. 3.465 3.465 0 VDD +0.3 VDDQ +0.3 0.8
(1)
Unit V V V V V V
5279 tbl 06
TA
(7)
o
VDDQ VSS VIH VIH VIL
o
o
W mA
NOTES: 1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle. 2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
5279 tbl 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. VDDQ terminals only. 4. Input terminals only. 5. I/O terminals only. 6. This is a steady-state DC parameter that applies after the power supplies have ramped up. Power supply sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp up. 7. TA is the "instant on" case temperature.
100 Pin TQFP Capacitance
(TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter
(1)
119 BGA Capacitance
(TA = +25C, f = 1.0MHz)
Max. 5 7 Unit pF pF
5279 tbl 07
Conditions VIN = 3dV VOUT = 3dV
Symbol CIN CI/O
Parameter(1) Input Capacitance I/O Capacitance
Conditions VIN = 3dV VOUT = 3dV
Max. 7 7
Unit pF pF
5279 tbl 07a
Input Capacitance I/O Capacitance
165 fBGA Capacitance
(TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 7 7
Unit pF pF
5279 tbl 07b
NOTE: 1. This parameter is guaranteed by device characterization, but not production tested.
6.42 4
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36
A6 A7 CE CS0 BW4 BW3 BW2 BW1 CS1 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3 I/O16 I/O17 VDDQ VSS I/O18 I/O19 I/O20 I/O21 VSS VDDQ I/O22 I/O23 VDD / NC(1) VDD NC VSS I/O24 I/O25 VDDQ VSS I/O26 I/O27 I/O28 I/O29 VSS VDDQ I/O30 I/O31 I/OP4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/OP2 I/O15 I/O14 VDDQ VSS I/O13 I/O12 I/O11 I/O10 VSS VDDQ I/O9 I/O8 VSS NC VDD ZZ(2) I/O7 I/O6 VDDQ VSS I/O5 I/O4 I/O3 I/O2 VSS VDDQ I/O1 I/O0 I/OP1
5279 drw 02
,
LBO A5 A4 A3 A2 A1 A0
NOTES: 1. Pin 14 can either be directly connected to VDD, or connected to an input voltage VIH, or left unconnected. 2. Pin 64 can be left unconnected and the device will always remain in active mode.
NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16
TQFP Top View
6.42 5
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 18
A6 A7 CE CS0 NC NC BW2 BW1 CS1 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC NC NC VDDQ VSS NC NC I/O8 I/O9 VSS VDDQ I/O10 I/O11 VDD / NC(1) VDD NC VSS I/O12 I/O13 VDDQ VSS I/O14 I/O15 I/OP2 NC VSS VDDQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A10 NC NC VDDQ VSS NC I/OP1 I/O7 I/O6 VSS VDDQ I/O5 I/O4 VSS NC VDD ZZ(2) I/O3 I/O2 VDDQ VSS I/O1 I/O0 NC NC VSS VDDQ NC NC NC
5279 drw 03
,
LBO A5 A4 A3 A2 A1 A0 NC
TQFP Top View
NOTES: 1. Pin 14 can either be directly connected to VDD, or connected to an input voltage VIH, or left unconnected. 2. Pin 64 can be left unconnected and the device will always remain in active mode.
NC VSS VDD NC NC A11 A12 A13 A14 A15 A16 A17
6.42 6
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36, 119 BGA
1 A B C D E F G H J K L M N P R T U VDDQ NC NC I/O16 I/O17 VDDQ I/O20 I/O22 VDDQ I/O24 I/O25 VDDQ I/O29 I/O31 NC NC VDDQ 2 A6 CS0 A7 I/OP3 I/O18 I/O19 I/O21 I/O23 VDD I/O26 I/O27 I/O28 I/O30 I/OP4 A5 NC NC/TMS(2) 3 A4 A3 A2 VSS VSS VSS BW3 VSS NC VSS BW4 VSS VSS VSS LBO A10 NC/TDI(2) 4 ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1 A0 VDD A11 NC/TCK(2) 5 A8 A9 A12 VSS VSS VSS BW 2 VSS NC VSS BW1 VSS VSS VSS VDD / NC(1) 6 A16 CS1 A15 I/OP2 I/O13 I/O12 I/O11 I/O9 VDD I/O6 I/O4 I/O3 I/O2 I/O0 A13 NC NC/TRST(2,3) 7 VDDQ NC NC I/O15 I/O14 VDDQ I/O10 I/O8 VDDQ I/O7 I/O5 VDDQ I/O1 I/OP1 NC ZZ(4) VDDQ
5279 drw 04
A14 NC/TDO(2)
,
Top View Pin Configuration 256K x 18, 119 BGA
1 A B C D E F G H J K L M N P R T U VDDQ NC NC I/O8 NC VDDQ NC I/O11 VDDQ NC I/O13 VDDQ I/O15 NC NC NC VDDQ 2 A6 CS0 A7 NC I/O9 NC I/O10 NC VDD I/O12 NC I/O14 NC I/OP2 A5 A10 3 A4 A3 A2 VSS VSS VSS BW2 VSS NC VSS VSS VSS VSS VSS LBO A15 4 ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1 A0 VDD NC 5 A8 A9 A13 VSS VSS VSS VSS VSS NC VSS BW1 VSS VSS VSS VDD / NC(1) A14 6 A16 CS1 A17 I/O7 NC I/O5 NC I/O3 VDD NC I/O1 NC I/O0 NC A12 A11
7 VDDQ NC NC NC I/O6 VDDQ I/O4 NC VDDQ I/O2 NC VDDQ NC I/OP1 NC ZZ(4)
,
NC/TMS(2) NC/TDI(2) NC/TCK(2)
NC/TDO(2) NC/TRST(2,3) VDDQ
5279 drw 05
NOTES: 1. R5 can either be directly connected to VDD, or connected to an input voltage VIH, or left unconnected. 2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating. 3. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD. 4. T7 can be left unconnected and the device will always remain in active mode.
Top View
6.42 7
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36, 165 fBGA
1 A B C D E F G H J K L M N P R NC(2) NC I/OP3 I/O17 I/O19 I/O21 I/O23 VDD(1) I/O25 I/O27 I/O29 I/O31 I/OP4 NC LBO 2 A7 A6 NC I/O16 I/O18 I/O20 I/O22 NC I/O24 I/O26 I/O28 I/O30 NC NC(2) NC(2) 3 CE1 CS0 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A5 A4 4 BW3 BW4 VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A2 A3 5 BW2 BW1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
NC/TRST
(3, 4)
6 CS1 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC
(2)
7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC/TDO(3) NC/TCK (3)
8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A10 A11
9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A13 A12
10 A8 A9 NC I/O15 I/O13 I/O11 I/O9 NC I/O7 I/O5 I/O3 I/O1 NC A14 A15
11 NC NC(2) I/OP2 I/O14 I/O12 I/O10 I/O8 ZZ(5) I/O6 I/O4 I/O2 I/O0 I/OP1 NC(2) A16
5279 tbl 17
NC/TDI(3) NC/TMS (3)
A1 A0
Pin Configuration 256K x 18, 165 fBGA
1 A B C D E F G H J K L M N P R NC
(2)
2 A7 A6 NC I/O8 I/O9 I/O10 I/O11 NC NC NC NC NC NC NC(2) NC(2)
3 CE1 CS0 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A5 A4
4 BW2 NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A2 A3
5 NC BW1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
NC/TRST
(3,4)
6 CS1 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC
(2)
7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC/TDO(3) NC/TCK (3)
8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A11 A12
9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A14 A13
10 A8 A9 NC NC NC NC NC NC I/O3 I/O2 I/O1 I/O0 NC A15 A16
11 A10 NC(2) I/OP1 I/O7 I/O6 I/O5 I/O4 ZZ(5) NC NC NC NC NC NC(2) A17
5279 tbl 17a
NC NC NC NC NC NC VDD
(1)
I/O12 I/O13 I/O14 I/O15 I/OP2 NC LBO
NC/TDI(3) NC/TMS(3)
A1 A0
NOTES: 1. H1 can either be directly connected to VDD, or connected to an input voltage VIH, or left unconnected. 2. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively. 3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating. 4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD. 5. H11 can be left unconnected and the device will always remain in active mode.
6.42 8
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V 5%)
Symbol |ILI| |ILZZ| |ILO| VOL VOH Parameter Input Leakage Current ZZ, LBO and JTAG Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VDD = Max., VIN = 0V to VDD VDD = Max., VIN = 0V to VDD VOUT = 0V to VDDQ, Device Deselected IOL = +8mA, VDD = Min. IOH = -8mA, VDD = Min. Min.
___
Max. 5 30 5 0.4
___
Unit A A A V V
5279 tbl 08
___ ___
___
2.4
NOTE: 1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1)
150MHz Symbol IDD ISB1 ISB2 IZZ Parameter Operating Power Supply Current CMOS Standby Power Supply Current Clock Running Power Supply Current Full Sleep Mode Supply Current Test Conditions Device Selected, Outputs Open, VDD = Max., VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2) Device Deselected, Outputs Open, VDD = Max., VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3) Device Deselected, Outputs Open, VDD = Max., VDDQ = Max., VIN > VHD or < VLD, f = fMAX(2,3) ZZ > VHD, VDD = Max. Com'l 295 30 105 30 Ind 305 35 115 35 133MHz Com'l 250 30 100 30 Ind 260 35 110 35 Unit mA mA mA mA
5279 tbl 09
NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing. 3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Conditions
(VDDQ = 3.3V)
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Timing Reference Levels AC Test Load 0 to 3V 2ns 1.5V 1.5V See Figure 1
5279 tbl 10
AC Test Load
I/O Z0 = 50
VDDQ/2 50 ,
5279 drw 06
Figure 1. AC Test Load
6 5 4 tCD 3 (Typical, ns) 2 1 20 30 50 80 100 Capacitance (pF) 200
5279 drw 07
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42 9
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1,3)
Operation Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. OE is an asynchronous input. 3. ZZ = low for this table.
Address Used None None None None None External External External External External External External Next Next Next Next Next Next Next Next Next Next Next Next Current Current Current Current Current Current Current Current Current Current Current Current
CE H L L L L L L L L L L L X X X X H H H H X X H H X X X X H H H H X X H H
CS0 X X L X L H H H H H H H X X X X X X X X X X X X X X X X X X X X X X X X
CS1 X H X H X L L L L L L L X X X X X X X X X X X X X X X X X X X X X X X X
ADSP X L L X X L L H H H H H H H H H X X X X H H X X H H H H X X X X H H X X
ADSC L X X L L X X L L L L L H H H H H H H H H H H H H H H H H H H H H H H H
ADV X X X X X X X X X X X X L L L L L L L L L L L L H H H H H H H H H H H H
GW X X X X X X X H H H H L H H H H H H H H H L H L H H H H H H H H H L H L
BWE X X X X X X X H L L L X H H X X H H X X L X L X H H X X H H X X L X L X
BWx X X X X X X X X H H L X X X H H X X H H L X L X X X H H X X H H L X L X
OE (2) X X X X X L H L L H X X L H L H L H L H X X X X L H L H L H L H X X X X
CLK -
I/O HI-Z HI-Z HI-Z HI-Z HI-Z DOUT HI-Z DOUT DOUT HI-Z DIN DIN DOUT HI-Z DOUT HI-Z DOUT HI-Z DOUT HI-Z DIN DIN DIN DIN DOUT HI-Z DOUT HI-Z DOUT HI-Z DOUT HI-Z DIN DIN DIN DIN
5279 tbl 11
6.42 10
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1, 2)
Operation Read Read Write all Bytes Write all Bytes Write Byte 1
(3) (3) (3) (3)
GW H H L H H H H H
BWE H L X L L L L L
BW1 X H X L L H H H
BW2 X H X L H L H H
BW3 X H X L H H L H
BW4 X H X L H H H L
5279 tbl 12
Write Byte 2 Write Byte 3 Write Byte 4
NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. BW3 and BW4 are not applicable for the IDT71V3578. 3. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table(1)
Operation(2) Read Read Write Deselected Sleep Mode OE L H X X X ZZ L L L L H I/O Status Data Out High-Z High-Z - Data In High-Z High-Z Power Active Active Active Standby Sleep
5279 tbl 13
NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1 A1 First Address Second Address Third Address Fourth Address (1) 0 0 1 1 A0 0 1 0 1 Sequence 2 A1 0 0 1 1 A0 1 0 1 0 Sequence 3 A1 1 1 0 0 A0 0 1 0 1 Sequence 4 A1 1 1 0 0 A0 1 0 1 0
5279 tbl 14
NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1 A1 First Address Second Address Third Address Fourth Address (1) 0 0 1 1 A0 0 1 0 1 Sequence 2 A1 0 1 1 0 A0 1 0 1 0 Sequence 3 A1 1 1 0 0 A0 0 1 0 1 Sequence 4 A1 1 0 0 1 A0 1 0 1 0
5279 tbl 15
NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42 11
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V 5%, Commercial and Industrial Temperature Ranges)
150MHz Symbol Parameter Min. Max. Min. 133MHz Max. Unit
tCYC tCH(1) tCL(1)
Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width
6.7 2.6 2.6
____
7.5 3 3
____
ns ns ns
____
____
____
____
Output Parameters
tCD tCDC tCLZ(2) tCHZ(2) tOE tOLZ(2) tOHZ(2) Clo ck High to Valid Data Clock High to Data Change Clock High to Output Active Clock High to Data High-Z Output Enable Access Time Output Enable Low to Output Active Output Enable High to Output High-Z
____
3.8
____
____
4.2
____
ns ns ns ns ns ns ns
1.5 0 1.5
____
1.5 0 1.5
____
____
____
3.8 3.8
____
4.2 4.2
____
0
____
0
____
3.8
4.2
Set Up Times
tSA tSS tSD tSW tSAV tSC Address Setup Time Address Status Setup Time Data In Setup Time Write Setup Time Address Advance Setup Time Chip Enable/Select Setup Time 1.5 1.5 1.5 1.5 1.5 1.5
____ ____ ____ ____ ____ ____
1.5 1.5 1.5 1.5 1.5 1.5
____ ____ ____ ____ ____ ____
ns ns ns ns ns ns
Hold Times
tHA tHS tHD tHW tHAV tHC Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Address Advance Hold Time Chip Enable/Select Hold Time 0.5 0.5 0.5 0.5 0.5 0.5
____ ____
0.5 0.5 0.5 0.5 0.5 0.5
____ ____
ns ns ns ns ns ns
____ ____ ____ ____
____ ____ ____ ____
Sleep Mode and Configuration Parameters
tZZPW tZZR(3) tCFG (4) ZZ Pulse Width ZZ Recovery Time Configuration Set-up Time 100 100 27
____
100 100 30
____
ns ns ns
5279 tbl 16
____
____
____
____
NOTES: 1. Measured as HIGH above VIH and LOW below VIL. 2. Transition is measured 200mV from steady-state. 3. Device must be deselected when powered-up from sleep mode. 4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
6.42 12
tCYC
CLK tCH tCL
tSS tHS
ADSP
(1)
ADSC tHA Ax tSW tHW Ay
tSA
ADDRESS
GW,BWE,BWx tHC tSAV tHAV
tSC
CE, CS1
(Note 3)
Timing Waveform of Pipelined Read Cycle(1,2)
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
6.42 13
tOE tCD tOHZ tCDC
O1(Ay) O2(Ay) O3(Ay)
ADV
ADV HIGH suspends burst
OE tOLZ tCLZ
O1(Ax)
(Burst wraps around to its initial state)
tCHZ
O4(Ay) O1(Ay) O2(Ay)
DATAOUT
Output Disabled Pipelined Read
Burst Pipelined Read
5279 drw 08
NOTES: 1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. ZZ input is LOW and LBO is Don't Care for this cycle. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
,
tCYC
CLK tCH tCL
(2)
tSS tHS
ADSP
tSA tHA Ax Ay tSW tHW Az
ADDRESS
GW
ADV
OE tSD tHD tOE tCD tCLZ O1(Ax) tOHZ I1(Ay) tOLZ
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
6.42 14
DATAIN
tCDC O1(Az) tCD O2(Az) O3(Az)
DATAOUT
Single Read
Pipelined Write
Pipelined Burst Read
5279 drw 09
NOTES: 1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH. 2. ZZ input is LOW and LBO is Don't Care for this cycle. 3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
,
tCYC
CLK tCH tCL
tSS tHS
ADSP
ADSC
tSA tHA Ax
GW is ignored when ADSP initiates a cycle and is sampled on the next clock rising edge
ADDRESS Ay Az tHW tSW
GW
tSC
tHC
CE, CS1 tSAV tHAV
(Note 3)
ADV
(ADV HIGH suspends burst)
Timing Waveform of Write Cycle No. 1 - GW Controlled(1,2,3)
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
6.42 15
I1(Ax) I2(Ay) tOHZ I1(Ay) I2(Ay) Burst Write Single Write
OE tSD I3(Ay) I4(Ay) I1(Az)
tHD
DATAIN
I2(Az)
I3(Az)
DATAOUT
O3(Aw)
O4(Aw)
Burst Read
Burst Write
5279 drw 10
,
NOTES: 1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle. 2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
tCYC
CLK tCH tCL
tSS tHS
ADSP
ADSC
tSA tHA Ax
BWE is ignored when ADSP initiates a cycle and is sampled on next clock rising edge
ADDRESS tHW tSW
Ay Az
BWE
BWx is ignored when ADSP initiates a cycle and is sampled on next clock rising edge
tHW tSW
BWx
tSC
tHC
CE, CS1 tSAV
(Note 3)
Timing Waveform of Write Cycle No. 2 - Byte Controlled(1,2,3)
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
6.42 16
(ADV suspends burst)
ADV
OE tSD I1(Ax) I2(Ay) tOHZ I1(Ay) I2(Ay) I3(Ay) I4(Ay) I1(Az)
tHD
DATAIN
I2(Az)
I3(Az)
DATAOUT Single Write
O3(Aw)
O4(Aw) Burst Write Extended Burst Write
5279 drw 11
Burst Read
NOTES: 1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle. 2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
,
tCYC
CLK tCH tCL
tSS
tHS
ADSP
ADSC tHA Ax Az
tSA
ADDRESS
GW tHC
tSC
CE, CS1
(Note 4)
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
6.42 17
tOE tOLZ
O1(Ax)
tZZPW
ADV
OE
DATAOUT
tZZR
ZZ
Single Read
Snooze Mode
5279 drw 12
,
NOTES: 1. Device must power up in deselected Mode 2. LBO is Don't Care for this cycle. 3. It is not necessary to retain the state of the input registers throughout the Power-down cycle. 4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
GW, BWE, BWx
CE, CS1
CS0
OE
DATAOUT
(Av)
(Aw)
(Ax)
(Ay)
5279 drw 14
,
NOTES: 1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle. 2. (Ax) represents the data for address Ax, etc. 3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
GW
CE, CS1
CS0
DATAIN
(Av)
(Aw)
(Ax)
(Ay)
(Az)
,
5279 drw 15
NOTES: 1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle. 2. (Ax) represents the data for address Ax, etc. 3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW. 4. For write cycles, ADSP and ADSC have different limitations.
6.42 18
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
tJF TCK tJCYC tJR
tJCL
tJCH
Device Inputs(1)/ TDI/TMS tJS Device Outputs(2)/ TDO tJH tJDC
tJRSR
tJCD x
M5279 drw 01
TRST(3) tJRST
NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST. 2. Device outputs = All device outputs except TDO. 3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical Characteristics(1,2,3,4)
Symbol tJCYC tJCH tJCL tJR tJF tJRST tJRSR tJCD tJDC tJS tJH Parameter JTAG Clock Input Period JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery JTAG Data Output JTAG Data Output Hold JTAG Setup JTAG Hold Min. 100 40 40
____ ____
Max.
____ ____ ____
Units ns ns ns ns ns ns ns ns ns ns ns
I5279 tbl 01
Scan Register Sizes
Register Name Instruction (IR) Bypass (BYR) JTAG Identification (JIDR) Boundary Scan (BSR) Bit Size 4 1 32 Note (1)
I5279 tbl 03
5(1) 5(1)
____ ____
50 50
____
20
____ ____ ____
NOTE: 1. The Boundary Scan Descriptive Language (BSDL) file for this device is available by contacting your local IDT sales representative.
0 25 25
NOTES: 1. Guaranteed by design. 2. AC Test Load (Fig. 1) on external output signals. 3. Refer to AC Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42 19
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions (SA Version only)
Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) Value 0x2 0x238, 0x23A 0x33 1 Reserved for version number. Defines IDT part number 71V3576SA and 71V3578SA, respectively. Allows unique identification of device vendor as IDT. Indicates the presence of an ID register.
I5279 tbl 02
Description
Available JTAG Instructions
Instruction EXTEST Description Forces contents of the bound ary scan cells onto the device outputs (1). Places the boundary scan registe r (BSR) between TDI and TDO. Places the boundary scan registe r (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) and outputs(1) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the bo undary scan cells via the TDI. Loads the JTAG ID register (JIDR) with the vendor ID code and places the register between TDI and TDO. Places the bypass register (BYR) be tween TDI and TDO. Forces all device o utput drivers to a High-Z state. OPCODE 0000
SAMPLE/PRELOAD
0001
DEVICE_ID HIGHZ RESERVED RESERVED RESERVED RESERVED CLAMP RESERVED RESERVED
0010 0011 0100
Several combinations are reserved. Do not use codes other than those identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP, VALIDATE and BYPASS instructions.
0101 0110 0111
Uses BYR. Forces contents of the bound ary scan cells onto the device outputs. Places the byp ass registe r (BYR) between TDI and TDO.
1000 1001 1010
Same as above. RESERVED RESERVED VALIDATE RESERVED BYPASS Automatically loaded into the instruction register whenever the TAP controller passes through the CAPTURE-IR state. The lower two bits '01' are mand ated by the IEEE std. 1149.1 specification. Same as above. The BYPASS instruction is used to truncate the boundary scan register as a single bit in length. 1011 1100 1101 1110 1111
I5279 tbl 04
NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.42 20
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Ordering Information
IDT XXX Device Type X S Power X Speed XX Package X Process/ Temperature Range
Blank I PF* BG BQ 150 133 S SA Blank Y 71V3576 71V3578
Commercial (0C to +70C) Industrial (-40C to +85C) 100-pin Plastic Thin Quad Flatpack (TQFP) 119 Ball Grid Array (BGA) 165 Fine Pitch Ball Grid Array (fBGA) Frequency in Megahertz Standard Power Standard Power with JTAG Interface First generation or current stepping Second generation die step
,
5279 drw 13
128K x 36 Pipelined Burst Synchronous SRAM with 3.3V I/O 256K x 18 Pipelined Burst Synchronous SRAM with 3.3V I/O
* Note: JTAG (SA version) is not available with 100-pin TQFP package.
Package Information
100-Pin Thin Quad Plastic Flatpack (TQFP) 119 Ball Grid Array (BGA) 165 Fine Pitch Ball Grid Array (fBGA) Information available on the IDT website
6.42 21
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Datasheet Document History
7/26/99 9/17/99 Updated to new format Revised ISB1 and IZZ for speeds 100-200MHz Revised tCDC (min.) at 166MHz Added 119 BGA package diagram Added Datasheet Document History Removed 166, 183, and 200MHz speed grade offerings (see IDT71V35761 and IDT71V35781) Added Industrial Temperature range offerings Added 100TQFP Package Diagram Outline Add capacitancce table for the BGA package; Add Industrial temperature to table; Insert note to Absolute Max Rating and Recommended Operating Temperature tables Add note to BGA pin configurations; corrected typo in pinout Add new package offering, 13 x 15mm fBGA Correct BG119 Package Diagram Outline Add note reference to BG119 pinout Add DNU reference note to BQ165 pinout Update BG119 Package Diagram Outline Dimensions Remove Preliminary Status Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST Updated 165 BGA table information from TBD to 7 Updated datasheet with JTAG information Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package)) requiring NC or connection to Vss. Added two pages of JTAG Specification, AC Electrical, Definitions and Instructions Removed old package information from the datasheet Updated ordering information with JTAG and Y stepping information. Added information regarding packages available IDT website.
12/31/99
Pg. 8 Pg. 11 Pg. 18 Pg. 20 Pg. 1, 8, 11, 19 Pg. 1, 4, 8, 11, 19 Pg.18 Pg. 4 Pg. 7
04/04/00
06/01/00 07/15/00 Pg. 20 Pg. 7 Pg. 8 Pg. 20 Pg. 8 Pg. 4 Pg. 1,2,3,5-9 Pg. 5-8 Pg. 19,20 Pg. 21-23 Pg. 24
10/25/00 04/22/03 06/30/03
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: sramhelp@idt.com 800-544-7726, x4033
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42 22

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